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LT3759 1 3759fb typical application features description wide input voltage range boost/sepic/inverting controller 2.5v to 36v input, 12v output sepic converter excellent for automotive 12v post regulator applications n wide v in range: 1.6v to 42v n positive or negative output voltage programming with a single feedback pin n pgood output voltage status report n accurate 50mv sense threshold voltage n programmable soft-start n programmable operating frequency (100khz to 1mhz) with one external resistor n synchronizable to an external clock n low shutdown current < 1a n intv cc regulator supplied from v in or drive n programmable input undervoltage lockout with hysteresis n datacom and industrial boost, sepic and inverting converters n distributed power supplies n portable electronic equipment n automotive l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot and no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7825665. the lt ? 3759 is a wide input range, current mode, dc/dc controller which is capable of regulating either positive or negative output voltages from a single feedback pin. it can be configured as a boost, sepic or inverting converter. the LT3759 drives a low side external n-channel power mosfet. an internal ldo regulator draws power from v in or drive to provide up to a 4.75v supply for the gate driver. the fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. the operating frequency of LT3759 can be set over a 100khz to 1mhz range with an external resistor, or can be synchronized to an external clock using the sync pin. the LT3759 features soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. a window comparator on the fbx pin reports via the pgood pin, providing output voltage status indication. the device is available in a 12-lead exposed pad msop package. efficiency vs output current output current (a) 0 efficiency (%) 90 95 100 1.5 2.5 3759 ta01b 85 0.5 1 2 80 75 v in = 12v LT3759 v in v in 2.5v to 36v c in 4.7f 4 41.2k 200khz 4.7f 2 gate sense drive fbx gnd intv cc en/uvlo pgood sync tie to gnd if not used rt ss vc l1a l1b 105k 118k 0.1f 7.5k 22nf 105k 5m 100k 4.7f v out 12v 0.5a, 2.5v v in 8v 2a, 8v < v in 36v 3759 ta01a c out2 47f 4 m1 15.8k + c out1 10f
LT3759 2 3759fb pin configuration absolute maximum ratings v in ............................................................................42v en/uvlo (note 2) .....................................................42v drive .......................................................................42v pgood ......................................................................42v intv cc ........................................................................8v gate .................................................................. (note 3) sync ..........................................................................8v vc, ss .........................................................................3v (note 1) 1 2 3 4 5 6 vc fbx ss rt sync pgood 12 11 10 9 8 7 en/uvlo v in drive intv cc gate sense top view mse package 12-lead plastic msop 13 gnd ja = 35c/w to 40c/w exposed pad (pin 13) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LT3759emse#pbf LT3759emse#trpbf 3759 12-lead plastic msop C40c to 125c LT3759imse#pbf LT3759imse#trpbf 3759 12-lead plastic msop C40c to 125c LT3759hmse#pbf LT3759hmse#trpbf 3759 12-lead plastic msop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ f or more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ rt ............................................................................1.5v sense ....................................................................0.3v fbx ................................................................. C3v to 3v operating junction temperature range (note 4) LT3759e/LT3759i .............................. C40c to 125c LT3759h ............................................ C40c to 150c storage temperature range .................. C65c to 150c
LT3759 3 3759fb electrical characteristics parameter conditions min typ max units v in operating voltage l 1.6 42 v v in shutdown i q en/uvlo < 0.4v en/uvlo = 1.15v 0.1 1 6 a a v in operating i q 350 450 a drive shutdown quiescent current en/uvlo < 0.4v en/uvlo = 1.15v 0.1 0.1 1 2 a a drive quiescent current (not switching) r t = 27.4k, drive = 6v 2.0 2.5 ma sense current limit threshold l 46 50 54 mv sense input bias current current out of pin C55 a error amplifier fbx regulation voltage (v fbx(reg) ) fbx > 0v fbx < 0v l l 1.580 C0.815 1.6 C0.80 1.620 C0.785 v v fbx pin input current fbx = 1.6v fbx = C0.8v C10 60 120 10 na na transconductance g m (i 2 /v fbx ) fbx = v fbx(reg) 240 s vc output impedance 5m fbx line regulation [v fbx(reg) /(v in ? v fbx(reg) )] 1.6v < v in < 42v, fbx >0 1.6v < v in < 42v, fbx <0 0.02 0.02 0.05 0.05 %/v %/v vc current mode gain (v vc /v sense ) 5v/v vc source current fbx = 0v, vc = 1.3v C13 a vc sink current fbx = 1.7v, vc = 1.3v fbx = C0.85v, vc = 1.3v 13 10 a a oscillator switching frequency r t = 27.4k to gnd, v fbx = 1.6v r t = 86.6k to gnd, v fbx = 1.6v r t = 6.81k to gnd, v fbx = 1.6v 270 300 100 1000 330 khz khz khz r t voltage fbx = 1.6v, C0.8v 1.2 v gate minimum off-time 170 200 ns gate minimum on-time 170 200 ns sync input low l 0.4 v sync input high l 1.5 v ss pull-up current ss = 0v, current out of pin l C14 C10.5 C7 a low dropout regulators (drive ldo and v in ldo) drive ldo regulation voltage drive = 6v l 4.6 4.75 4.9 v v in ldo regulation voltage drive = 0v l 3.6 3.75 3.9 v drive ldo current limit intv cc = 4v 60 ma v in ldo current limit drive = 0v, intv cc = 3v 60 ma drive ldo load regulation (v intvcc /v intvcc ) 0 < i intvcc < 20ma, drive = 6v C1 C0.6 % v in ldo load regulation (v intvcc /v intvcc ) drive = 0v, 0 < i intvcc < 20ma C1 C0.6 % drive ldo line regulation [v intvcc /(v intvcc ? v in )] 1.6v < v in < 42v, drive = 6v 0.03 0.07 %/v v in ldo line regulation [v intvcc /(v intvcc ? v in )] drive = 0v, 5v < v in < 42v 0.03 0.07 %/v drive ldo dropout voltage (v drive C v intvcc ) drive = 4v, i intvcc = 20ma l 190 400 mv the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, en/uvlo = 12v, intv cc = 4.75v, unless otherwise noted.
LT3759 4 3759fb parameter conditions min typ max units v in ldo dropout voltage (v in C v intvcc )v in = 3v, drive = 0v, i intvcc = 20ma l 190 400 mv intv cc undervoltage lockout threshold falling 1.3 1.45 v intv cc current in shutdown en/uvlo = 0v 22 a logic en/uvlo threshold voltage falling l 1.17 1.22 1.27 v en/uvlo rising hysteresis 20 mv en/uvlo input low voltage i vin < 1a 0.4 v en/uvlo pin bias current low en/uvlo = 1.15v 1.8 2.2 2.6 a en/uvlo pin bias current high en/uvlo = 1.30v 10 100 na fbx power good threshold voltage fbx > 0v, pgood falling fbx < 0v, pgood falling v fbx(reg) C 0.08 v fbx(reg) + 0.04 v v fbx overvoltage threshold fbx > 0v, pgood rising fbx < 0v, pgood rising v fbx(reg) + 0.12 v fbx(reg) C 0.06 v v pgood output low (v ol )i pgood = 250a 210 300 mv pgood leakage current pgood = 42v 1 a intv cc minimum voltage to enable pgood function l 2.4 2.7 3.0 v intv cc minimum voltage to enable sync function l 2.4 2.7 3.0 v nmos gate drivers gate output rise time (t r )c l = 3300pf 20 ns gate output fall time (t f )c l = 3300pf 20 ns gate output low (v ol ) 0.05 v gate output high (v oh )i n t v cc C 0.05 v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, en/uvlo = 12v, intv cc = 4.75v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: for v in below 4v, the en/uvlo pin must not exceed v in for proper operation. note 3: this pin is for switching purposes. do not tie directly to a supply. note 4: the LT3759e is guaranteed to meet performance specifications from the 0c to 125c operating junction temperature range. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3759i is guaranteed over the full C40c to 125c operating junction temperature range. the LT3759h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 5: the LT3759 is tested in a feedback loop which servos v fbx to the reference voltages (1.6v and C0.8v) with the vc pin forced to 1.3v. note 6: rise and fall times are measured at 10% and 90% levels.
LT3759 5 3759fb typical performance characteristics dynamic quiescent current vs switching frequency r t vs switching frequency normalized switching frequency vs fbx voltage switching frequency vs temperature sense current limit threshold vs temperature sense current limit threshold vs duty cycle fbx positive regulation voltage vs temperature fbx negative regulation voltage vs temperature quiescent current vs temperature switching frequency (khz) 0 i q (ma) 15 20 25 600 1000 3759 g04 10 200 400 800 5 0 i q (v in ) i q (drive) c l = 3300pf, drive = 6v switching frequency (khz) 0 r t (k) 60 50 80 70 100 90 600 1000 3759 g05 40 30 200100 400 800 700 300 500 900 20 10 0 fbx voltage (v) C0.8 normalized frequency (%) 80 60 120 100 1.6 3759 g06 40 C0.4 0.8 0 0.4 1.2 20 0 temperature (c) C75 fbx regulation voltage (v) 1.61 1.62 0 150 3759 g01 1.60 C50 C25 25 50 75 100 125 1.59 1.58 temperature (c) C75 fbx regulation voltage (v) C0.79 C0.78 0 150 3759 g02 C0.80 C50 C25 25 50 75 100 125 C0.81 C0.82 temperature (c) C75 i q (ma) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 150 3759 g03 C50 C25 25 50 75 100 125 i q (drive) i q (v in ) v in = 12v drive = 6v temperature (c) C75 sense threshold (mv) 53 52 51 50 49 48 47 0 150 3759 g08 C50 C25 25 50 75 100 125 duty cycle (%) 0 sense threshold (mv) 50 48 51 53 52 100 3759 g09 49 20 60 40 80 47 temperature (c) C75 switching frequency (khz) 350 325 300 275 250 0 150 3759 g07 C50 C25 25 50 75 100 125 r t = 27.4k t a = 25c, unless otherwise noted.
LT3759 6 3759fb typical performance characteristics intv cc vs temperature intv cc load regulation intv cc line regulation intv cc dropout voltage vs current, temperature gate driver rise and fall time vs c l gate driver rise and fall time vs intv cc en/uvlo threshold vs temperature gate minimum on- and off-times vs temperature en/uvlo hysteresis current vs temperature c l (nf) 0 time (ns) 70 60 50 40 30 20 1512 3759 g17 10 6 3 9 0 rise time fall time intv cc = 4.75v intc cc (v) 2 time (ns) 25 20 15 10 5 5 4 4.5 3759 g18 3 2.5 3.5 0 rise time fall time c l = 3300pf temperature (c) C75 en/uvlo voltage (v) 1.27 1.25 1.23 1.21 1.19 1.17 0 150 3759 g10 C50 C25 25 50 75 100 125 en/uvlo rising en/uvlo falling temperature (c) C75 en/uvlo (a) 2.4 2.2 2.0 1.8 1.6 0 150 3759 g12 C50 C25 25 50 75 100 125 intv cc load (ma) 0 intv cc voltage (v) 4.0 3.5 6.0 5.5 5.0 4.5 25 3759 g14 2.5 3.0 5 15 10 20 2.0 drive ldo v in ldo (drive = 0v) intv cc load (ma) 0 dropout voltage (mv) 200 400 300 25 3759 g16 100 5 15 10 20 0 v in = 12v drive = 4v 150c 25c C55c temperature (c) C75 intv cc (v) 5.0 4.8 4.6 4.4 4.0 3.8 4.2 3.6 0 150 3759 g13 C50 C25 25 50 75 100 125 drive ldo v in ldo t a = 25c, unless otherwise noted. temperature (c) C75 minimum on/off time (ns) 200 190 180 170 160 150 140 130 0 150 3759 g11 C50 C25 25 50 75 100 125 minimum off time minimum on time v in (v) 0 intv cc voltage (v) 5.0 4.5 4.0 45 35 40 3759 g15 3.5 5 15 10 20 3025 3.0 drive ldo v in ldo
LT3759 7 3759fb pin functions drive: drive ldo supply pin. this pin can be connected to either v in or a quasi-regulated voltage supply such as a dc converter output. this pin must be bypassed with a minimum of 1f capacitor placed close to the pin. tie this pin to v in if not used. en/uvlo: shutdown and undervoltage detect pin. an accurate 1.22v (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2.2a pull-down current. an undervoltage condition resets soft- start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. fbx: voltage regulation feedback pin for positive or negative outputs. connect this pin to a resistor divider between the output and gnd. fbx is the input of two error amplifiersone configured to regulate a positive output; the other, a negative output. depending upon topology selected, switching causes the output to ramp positive or negative. the appropriate amplifier takes control while the other becomes inactive. additionally fbx is input for two window comparators that indicate through the pgood pin when the output is within 5% of the regulation volt- ages. fbx also modulates the switching frequency during start-up and fault conditions when fbx is close to gnd. gate: n-channel fet gate driver output. switches between intv cc and gnd. driven to gnd when ic is shut down, during thermal lockout or when intv cc is below undervoltage threshold. gnd: exposed pad. solder the exposed pad directly to ground plane. intv cc : regulated supply for internal loads and gate driver. regulated to 4.75v if powered from drive or regulated to 3.75v if powered from v in . the intv cc pin must be bypassed with a minimum of 4.7f capacitor placed close to the pin. pgood : output ready status pin. an open-collector pull down on pgood asserts when intv cc is greater than 2.7v and the fbx voltage is within 5% (80mv if v fbx = 1.6v or 40mv if v fbx = C0.8v) of the regulation voltage. rt: switching frequency adjustment pin. set the frequency using a resistor to gnd. do not leave the rt pin open. sense: the current sense input for the control loop. kelvin connect this pin to the positive terminal of the switch current sense resistor in the source of the n-fet. the negative terminal of the current sense resistor should be connected to gnd plane close to the ic. ss: soft-start pin. this pin modulates compensation pin voltage (vc) clamp. the soft-start interval is set with an external capacitor. the pin has a 10a (typical) pull-up current source to an internal 2.5v rail. the soft-start pin is reset to gnd by an en/uvlo undervoltage condition, an intv cc undervoltage condition or an internal thermal lockout. sync: frequency synchronization pin. used to synchronize the internal oscillator to an outside clock. if this feature is used, an r t resistor should be chosen to program a switch- ing frequency 20% slower than sync pulse frequency. tie the sync pin to gnd if this feature is not used. this signal is ignored during fb frequency foldback or when intv cc is less than 2.7v. vc: error amplifier compensation pin. used to stabilize the voltage loop with an external rc network. v in : supply pin for internal leads and the v in ldo regulator of intv cc . must be locally bypassed with a minimum of 1f capacitor placed close to this pin.
LT3759 8 3759fb block diagram m1 1.22v 1.2v 2.5v c in c vcc intv cc drive v in r sense v isense + i s1 2a 10 9 8 1 12 en/uvlo bandgap reference tsd ~165?c a10 q3 vc v c bg_low uvlo i s2 10a i s3 c c1 c c2 r c driver slope sense gnd gate 50mv sr1 + C ramp generator + C rq s 2.5v rt r t ss c ss sync freq foldback 1.25v fbx pgood fbx q4 1.6v C0.8v + C + C 2 6 3 5 4 + C + C 7 13 ramp pwm comparator frequency foldback 100khz ~ 1mhz oscillator r1 r2 l2 fbx d1 c dc v out c out2 c out1 t + 3759 f01 a1 a2 1.72v C0.86v + C + C a11 a12 + C a3 1.25v freq prog C + + q1 a4 a5 a6 g5 g6 a7 q2 g4 r3r4 v in 11 internal bias generator drive ldo current limit internal bias current limit v in ldo a8 + C g8 1.52v C0.76v + C + C a13 a14 g7 2.7v a15 + C g2 g1 t l1 bg figure 1. LT3759 block diagram working as a sepic converter
LT3759 9 3759fb applications information main control loop the LT3759 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. operation can be best understood by referring to the block diagram in figure 1. the start of each oscillator cycle sets the sr latch (sr1) and turns on the external power mosfet switch m1 through driver g2. the switch current flows through the external current sensing resistor r sense and generates a voltage proportional to the switch current. this current sense voltage v isense (amplified by a5) is added to a stabilizing slope compensation ramp and the resulting sum (slope) is fed into the positive terminal of the pwm comparator a7. when slope exceeds the level at the negative input of a7 (vc pin), sr1 is reset, turning off the power switch. the level at the negative input of a7 is set by the error amplifier a1 (or a2) and is an amplified version of the difference between the feedback voltage (fbx pin) and the reference voltage (1.6v or C0.8v, depending on the configuration). in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the LT3759 has a switch current limit function. the current sense voltage is input to the current limit comparator a6. if the sense pin voltage is higher than the sense current limit threshold v sense(max) (50mv, typical), a6 will reset sr1 and turn off m1 immediately. the LT3759 is capable of generating either positive or nega- tive output voltage with a single fbx pin. it can be configured as a boost or sepic converter to generate positive output voltage, or as an inverting converter to generate negative output voltage. when configured as a sepic converter, as shown in figure 1, the fbx pin is pulled up to the internal bias voltage of 1.6v by a voltage divider (r1 and r2) connected from v out to gnd. comparator a2 becomes inactive and comparator a1 performs the inverting amplification from fbx to vc. when the LT3759 is in an inverting configuration, the fbx pin is pulled down to C0.8v by a voltage divider connected from v out to gnd. comparator a1 becomes inactive and comparator a2 performs the noninverting amplification from fbx to vc. the LT3759 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. an overvoltage comparator a11 (with 40mv hysteresis) senses when the fbx pin voltage exceeds the positive regulated voltage (1.6v) by 7.5% and turns off m1. similarly, an overvoltage comparator a12 (with 20mv hysteresis) senses when the fbx pin voltage exceeds the negative regulated voltage (C0.8v) by 7.5% and turns off m1. both reset pulses are sent to the main rs latch (sr1) through g6 and g5. the external power mosfet switch m1 is actively held off for the duration of an output overvoltage condition. programming turn-on and turn-off thresholds with en/uvlo pin the en/uvlo pin controls whether the LT3759 is enabled or is in shutdown state. a micropower 1.22v reference, a comparator a10 and controllable current source i s1 allow the user to accurately program the supply voltage at which the ic turns on and off. the falling value can be accurately set by the resistor dividers r3 and r4. when en/uvlo is above 0.7v, and below the 1.22v threshold, the small pull-down current source i s1 (typical 2a) is active. the purpose of this current is to allow the user to program the rising hysteresis. the block diagram of the comparator and the external resistors is shown in figure 1. the typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: v vin(falling) = 1.22 ? (r3 + r4) r4 v vin(rising) = 2a ? r3 + v in(falling) for applications where the en/uvlo pin is only used as a logic input, the en/uvlo pin can be connected directly to the input voltage v in for always-on operation. intv cc low dropout voltage regulators the LT3759 features two internal low dropout (ldo) volt- age regulators (v in ldo and drive ldo) powered from different supplies (v in and drive respectively). both ldos regulate the internal intv cc supply which powers the gate driver and the internal loads, as shown in figure 1. both regulators are designed so that current does not flow from intv cc to the ldo input under a reverse bias condition. drive ldo regulates the intv cc to 4.75v, while v in ldo
LT3759 10 3759fb regulates the intv cc to 3.75v. v in ldo is turned off when the intv cc voltage is greater than 3.75v (typical). both ldos can be turned off if the intv cc pin is driven by a supply of 4.75v or higher but less than 8v (the intv cc maximum voltage rating is 8v). a table of the ldo sup- ply and output voltage combination is shown in table 1. table 1. ldos supply and output voltage combination (assuming that the ldo dropout voltage is 0.15v) supply voltages ldo output ldo status (note 7) v in drive intv cc v in 3.9v v drive < v in v in C 0.15v #1 is on v drive = v in v in C 0.15v #1 #2 are on v in < v drive < 4.9v v drive C 0.15v #2 is on 4.9v v drive 42v 4.75v #2 is on 3.9v < v in 42v v drive < 3.9v 3.75v #1 is on v drive = 3.9v 3.75v #1 #2 are on 3.9v < v drive < 4.9v v drive C 0.15v #2 is on 4.9v v drive 42v 4.75v #2 is on note 7: #1 is v in ldo and #2 is drive ldo the drive pin provides flexibility to power the gate driver and the internal loads from a supply that is available only when the switcher is enabled and running. if not used, the drive pin should be tied to v in . the intv cc pin must be bypassed to ground immediately adjacent to the intv cc pin with a minimum of 4.7f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. if a low input voltage operation is expected (v in is 3v or less), low threshold mosfets should be used. the LT3759 contains an undervoltage lockout comparator a8 for the internal intv cc supply. the intv cc undervoltage (uv) threshold is 1.3v (typical), with 100mv hysteresis, to ensure that the mosfets have sufficient gate drive voltage before turning on. the logic circuitry within the LT3759 is also powered from the internal intv cc supply. when intv cc is below the uv threshold, the gate pin will be forced to gnd and the soft-start operation will be triggered. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet. the on-chip power dissipation can be a significant con- cern when a large power mosfet is being driven at a high frequency and the v in voltage is high. it is important to limit the power dissipation with proper selection of a mosfet and/or an operating frequency so the LT3759 does not exceed its maximum junction temperature rating. the junction temperature t j can be estimated using the following equations: t j = t a + p ic ? ja t a = ambient temperature ja = junction-to-ambient thermal resistance p ic = ic power consumption = v in ? (i q + i drive ) (assume the drive pin is connected to v in supply) i q = v in operation i q = 1.8ma i drive = average gate drive current = f ? q g f = switching frequency q g = power mosfet total gate charge the LT3759 uses packages with an exposed pad for en- hanced thermal conduction. with proper soldering to the exposed pad on the underside of the package and a full copper plane underneath the device, thermal resistance ( ja ) will be about 40c/w for the mse package. the LT3759 has an internal intv cc i drive current limit function to protect the ic from excessive on-chip power dissipation. if i drive reaches the current limit, intv cc voltage will fall and may trigger the soft-start. there is a trade-off between the operating frequency and the size of the power mosfet (q g ) in order to maintain a reliable ic junction temperature. prior to lowering the operating frequency, however, be sure to check with power mosfet manufacturers for their most recent low q g , low r ds(on) devices. power mosfet manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. operating frequency and synchronization the choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. low frequency applications information
LT3759 11 3759fb operation improves efficiency by reducing gate drive cur- rent and mosfet and diode switching losses. however, lower frequency operation requires a physically larger loop inductor. switching frequency also has implications for loop compensation. the LT3759 uses a constant-frequency architecture that can be programmed over a 100khz to 1mhz range with a single external resistor from the rt pin to ground, as shown in figure 1. the rt pin must have an external resistor to gnd for proper operation of the LT3759. a table for selecting the value of r t for a given operating frequency is shown in table 2. table 2. timing resistor (r t ) value oscillator frequency (khz) r t (k) 100 86.6 200 41.2 300 27.4 400 21.0 500 16.5 600 13.7 700 11.5 800 9.76 900 8.45 1000 6.81 the switching frequency of the LT3759 can be synchronized to the positive edge of an external clock source. by provid- ing a digital clock signal into the sync pin, the LT3759 will operate at the sync clock frequency. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. the sync pulse should have a minimum pulse width of 200ns. tie the sync pin to gnd if this feature is not used. duty cycle consideration switching duty cycle is a key variable defining converter operation. as such, its limits must be considered. minimum on-time is the smallest time duration that the LT3759 is capable of turning on the power mosfet. this time is generally about 170ns (typical) (see minimum on-time in the electrical characteristics table). in each switching cycle, the LT3759 keeps the power switch off for at least 170ns (typical) (see minimum off-time in the electrical characteristics table). the minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: minimum duty cycle = minimum on-time ? frequency maximum duty cycle = 1 C (minimum off-time ? frequency) programming the output voltage the output voltage (v out ) is set by a resistor divider, as shown in figure 1. the positive v out and negative v out are set by the following equations: v out(positive) = 1.6v ? 1 + r2 r1 ? ? ? ? ? ? v out(negative) = C0.8v ? 1 + r2 r1 ? ? ? ? ? ? the resistors r1 and r2 are typically chosen so that the error caused by the current flowing into the fbx pin dur- ing normal operation is less than 1% (this translates to a maximum value of r1 at about 158k). soft-start the LT3759 contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. LT3759 addresses this mechanism with the ss pin. as shown in figure 1, the ss pin reduces the power mosfet current by pulling down the vc pin through q2. in this way the ss allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. applications information
LT3759 12 3759fb besides start-up, soft-start can also be triggered by intv cc undervoltage lockout and/or thermal lockout, which causes the LT3759 to stop switching immediately. the ss pin will be discharged by q3. when all faults are cleared and the ss pin has been discharged below 0.2v, a 10a current source i s2 starts charging the ss pin, initiating a soft-start operation. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 1.25v 10a fbx frequency foldback when v out is very low during start-up or a short-circuit fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. the minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switch- ing frequency. so, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. to prevent the switch peak currents from exceeding the programmed value, the LT3759 contains a frequency foldback function to reduce the switching frequency when the fbx voltage is low (see the normal- ized switching frequency vs fbx graph in the typical performance characteristics section). some frequency foldback waveforms are shown in the typical applications section. the frequency foldback func- tion prevents i l from exceeding the programmed limits because of the minimum on-time. during frequency foldback, external clock synchronization is disabled to allow the frequency reducing operation to function properly. thermal lockout if the LT3759 die temperature reaches 165c (typical), the part will go into thermal lockout. the power switch will be turned off. a soft-start operation will be triggered. the part will be enabled again when the die temperature has dropped by 5c (nominal). loop compensation loop compensation determines the stability and transient performance. the LT3759 uses current mode control to regulate the output which simplifies loop compensation. the optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). to compensate the feedback loop of the LT3759, a series resistor-capacitor network is usually connected from the vc pin to gnd. figure 1 shows the typical vc compensation network. for most applications, the capacitor should be in the range of 470pf to 22nf, and the resistor should be in the range of 5k to 50k. a small capacitor is often connected in paral- lel with the rc compensation network to attenuate the vc voltage ripple induced from the output voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 10pf to 100pf. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. sense pin programming for control and protection, the LT3759 measures the power mosfet current by using a sense resistor (r sense ) between gnd and the mosfet source. figure 2 shows a typical wave-form of the sense voltage (v sense ) across the sense resistor. it is important to use kelvin traces between the sense pin and r sense , and to place the ic gnd as close as possible to the gnd terminal of the r sense for proper operation. figure 2. the sense voltage during a switching cycle applications information 3759 f02 v sense(peak) v sense = ? v sense(max) v sense t dt s v sense(max) t s
LT3759 13 3759fb due to the current limit function of the sense pin, r sense should be selected to guarantee that the peak current sense voltage v sense(peak) during steady state normal opera- tion is lower than the sense current limit threshold (see the electrical characteristics table). given a 20% margin, v sense(peak) is set to be 40mv. then, the maximum switch ripple current percentage can be calculated using the fol- lowing equation: c= d v sense 40mv - 0.5 ? d v sense is used in subsequent design examples to calculate inductor value. v sense is the ripple voltage across r sense . the LT3759 has internal slope compensation to stabilize the control loop against sub-harmonic oscillation. when the LT3759 operates at a high duty cycle in continuous conduction mode, the sense voltage ripple v sense (re- fer to figure 2) needs to be limited to ensure the internal slope compensation is sufficient to stabilize the control loop. figure 3 shows the maximum allowed v sense over the duty cycle. it is recommended to check and ensure v sense is below the curve at the highest duty cycle. figure 4. the rc filter on sense pin applications information the LT3759 switching controller incorporates 100ns timing interval to blank the ringing on the current sense signal immediately after m1 is turned on. this ringing is caused by the parasitic inductance and capacitance of the pcb trace, the sense resistor, the diode, and the mosfet. the 100ns timing interval is adequate for most of the LT3759 applications. in the applications that have very large and long ringing on the current sense signal, a small rc filter can be added to filter out the excess ringing. figure 4 shows the rc filter on sense pin. it is usually sufficient to choose 22 for r flt and 2.2nf to 10nf for c flt . keep r flts resistance low. remember that there is 50a (typi- cal) flowing out of the sense pin. adding r flt will affect the sense current limit threshold: v sense _ilim = 50mv ? 50a ?r flt c flt 3759 f04 LT3759 r flt r sense m 1 sense gate gnd figure 3. the maximum allowed sense voltage ripple vs duty cycle duty cycle 0 maximum v sense (mv) 40 30 60 50 1 3759 f03 20 0.1 0.5 0.6 0.7 0.2 0.3 0.4 0.8 0.9 10 0 application circuits the LT3759 can be configured as different topologies. the design procedure for component selection differs somewhat between these topologies. the first topology to be analyzed will be the boost converter, followed by the flyback sepic and inverting converters. boost converter: switch duty cycle and frequency the LT3759 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost con- verters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short-circuit protected, please refer to the applications information section covering sepic converters.
LT3759 14 3759fb the selection of switching frequency is the starting point. the maximum frequency that can be used is based on the maximum duty cycle. the conversion ratio as a function of duty cycle is: v out v in = 1 1 ? d in continuous conduction mode (ccm). the equations that follow assume ccm operation. for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out the alternative to ccm, discontinuous conduction mode (dcm) is not limited by duty cycle to provide high con- version ratios at a given frequency. the price one pays is reduced efficiency and substantially higher switching current. boost converter: inductor and sense resistor selection for the boost topology, the maximum average inductor current is: i l(max) = i o(max ) ? 1 1 ? d max then, the ripple current can be calculated by: d i l =c?i l(max) =c?i o(max) ? 1 1- d max the constant in the preceding equation represents the percentage peak-to-peak ripple current in the inductor, relative to i l(max) . the inductor ripple current has a direct effect on the choice of inductor value. choosing smaller values of i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of i l provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses. it is recommended that falls within the range of 0.2 to 0.6. the peak and rms inductor current are: i l(peak) = i l(max) ?1 + 2 ? ? ? ? ? ? i l(rms) = i l(max) ?1 + 2 12 the inductor used with the LT3759 should have a saturation current rating appropriate to the maximum switch current selected with the r sense resistor. choose an inductor value based on operating frequency, input and output voltage to provide a current mode ramp on sense during the switch on-time of approximately 10mv magnitude. the following equation is useful to estimate the inductor value for continuous conduction mode operation: l = r sense ?v in(min) 0.01v ? f osc ?d max set the sense voltage at i l(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 40mv i l(peak) boost converter: power mosfet selection important parameters for the power mosfet include the drain-source voltage rating (v ds ), the threshold voltage (v gs(th) ), the on-resistance (r ds(on) ), the gate to source and gate to drain charges (q gs and q gd ), the maximum drain current (i d(max) ) and the mosfets thermal resis- tances (r jc and r ja ). the power mosfet will see full output voltage, plus a diode forward voltage, and any additional ringing across its drain-to-source during its off-time. it is recommended applications information
LT3759 15 3759fb to choose a mosfet whose bv dss is higher than v out by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the mosfet in a boost converter is: p fet = i 2 l(max) ?r ds(on) ? d max + v 2 out ? i l(max) ? c rss ? f 1a the first term in the preceding equation represents the conduction losses in the devices, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. for maximum efficiency, r ds(on) and c rss should be minimized. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a ? p fet ? ja = t a + p fet ?( jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. the average forward current in normal operation is equal to the output current, and the peak current is equal to: i d(peak ) = i l(peak) = 1 + 2 ? ? ? ? ? ? ?i l(max) it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max ) ?v d and the diode junction temperature is: t j = t a ? p d ? r ja the r ja to be used in this equation normally includes the r jc for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. boost converter: output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform for a typical boost converter is illustrated in figure 5. the choice of component(s) begins with the maximum applications information figure 5. the output ripple waveform of a boost converter v out (ac) t on )v esr ringing due to total inductance (board + cap) )v cout 3759 f05 t off acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step v esr and charging/discharging v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between v esr and v cout . this percentage ripple will
LT3759 16 3759fb change, depending on the requirements of the applica- tion, and the following equations can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the fol- lowing equation: esr cout 0.01? v out i d(peak ) for the bulk c component, which also contributes 1% to the total ripple: c out i o(max ) 0.01? v out ?f the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 5. the rms ripple current rating of the output capacitor can be determined using the following equation: i rms(cout) i o(max ) ? d max 1 ? d max multiple capacitors are often paralleled to meet esr requirements. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the required rms current rating. additional ceramic capaci- tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current wave- form is continuous. the input voltage source impedance determines the size of the input capacitor, which is typi- cally in the range of 10f to 100f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost converter is: i rms(cin) = 0.3 ? d i l flyback converter applications the LT3759 can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. figure 6 shows a simplified flyback converter. the flyback converter has a very low parts count for mul- tiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. however, it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. the flyback converter is commonly used for an output power of less than 50w. the flyback converter can be designed to operate either in continuous or discontinuous mode. compared to con- tinuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compen- sation, and the disadvantage of higher peak-to-average current and lower efficiency. in the high output voltage applications, the flyback converters can be designed to operate in discontinuous mode to avoid using large transformers. applications information figure 6. a simplified flyback converter r sense n p :n s v in c in c sn v sn l p d suggested rcd snubber i d i sw v ds 3759 f06 gate gnd LT3759 sense l s m + C + C r sn d sn C + + c out +
LT3759 17 3759fb flyback converter: switch duty cycle and turns ratio the flyback converter conversion ratio in the continuous mode operation is: v out v in = n s n p ? d 1 ? d where n s /n p is the second to primary turns ratio. figure 7 shows the waveforms of the flyback converter in discontinuous mode operation. during each switching period t s , three subintervals occur: dt s , d2t s , d3t s . during dt s , m is on, and d is reverse-biased. during d2t s , m is off, and l s is conducting current. both l p and l s currents are zero during d3t s . the flyback converter conversion ratio in the discontinu- ous mode operation is: v out v in = n s n p ? d d2 according to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. the selections of the duty cycle and the turns ratio are somewhat iterative processes, due to the number of variables involved. the user can choose either a duty cycle or a turns ratio as the start point. the following trade-offs should be considered when select- ing the switch duty cycle or turns ratio, to optimize the converter performance. a higher duty cycle affects the flyback converter in the following aspects: ? lower mosfet rms current i sw(rms) , but higher mosfet v ds peak voltage ? lower diode peak reverse voltage, but higher diode rms current i d(rms) ? higher transformer turns ratio (n p /n s ) the choice, d d + d2 = 1 3 (for discontinuous mode operation with a given d3) gives the power mosfet the lowest power stress (the product of rms current and peak voltage). however, in the high output voltage applications, a higher duty cycle may be adopted to limit the large peak reverse voltage of the diode. the choice, d d + d2 = 2 3 (for discontinuous mode operation with a given d3) gives the diode the lowest power stress (the product of rms current and peak voltage). an extreme high or low duty cycle results in high power stress on the mosfet or diode, and reduces efficiency. it is recommended to choose a duty cycle, d, between 20% and 80%. applications information figure 7. waveforms of the flyback converter in discontinuous mode operation 3759 f07 i sw v ds i d t dt s d2t s d3t s i sw(max) i d(max) t s
LT3759 18 3759fb applications information flyback converter: transformer design for discontinuous mode operation the transformer design for discontinuous mode of opera- tion is chosen as presented here. according to figure 7, the minimum d3 (d3 min ) occurs when the converter has the minimum v in and the maximum output power (p out ). choose d3 min to be equal to or higher than 10% to guarantee the converter is always in discontinuous mode operation (choosing higher d3 allows the use of low inductances, but results in a higher switch peak current). the user can choose a d max as the start point. then, the maximum average primary currents can be calculated by the following equation: i lp(max) = i sw(max) = p out(max) d max ?v in(min) ? where is the converter efficiency. if the flyback converter has multiple outputs, p out(max) is the sum of all the output power. the maximum average secondary current is: i ls(max) = i d(max ) = i out(max) d2 where: d2 = 1 C d max C d3 the primary and secondary rms currents are: i lp(rms) = 2?i lp(max) ? d max 3 i ls(rms) = 2?i ls(max) ? d2 3 according to figure 7, the primary and secondary peak currents are: i lp(peak) = i sw(peak) = 2 ? i lp(max) i ls(peak) = i d(peak) = 2 ? i ls(max) the primary and second inductor values of the flyback converter transformer can be determined using the fol- lowing equations: l p = d 2 max ?v 2 in(min) ? 2?p out(max) ?f osc l s = d2 2 ?(v out + v d ) 2?i out(max) ?f osc the primary to second turns ratio is: n p n s = l p l s flyback converter: snubber design transformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the mos- fet turn-off. this is increasingly prominent at higher load currents, where more stored energy must be dissipated. in some cases a snubber circuit will be required to avoid overvoltage breakdown at the mosfets drain node. there are different snubber circuits, and application note 19 is a good reference on snubber design. an rcd snubber is shown in figure 6. the snubber resistor value (r sn ) can be calculated by the following equation: r sn = 2? v 2 sn ? v sn ?v out ? n p n s i 2 sw(peak) ?l lk ?f osc where v sn is the snubber capacitor voltage. a smaller v sn results in a larger snubber loss. a reasonable v sn is 2 to 2.5 times of: v out ?n p n s
LT3759 19 3759fb applications information l lk is the leakage inductance of the primary winding, which is usually specified in the transformer characteristics. l lk can be obtained by measuring the primary inductance with the secondary windings shorted. the snubber capacitor value (c cn ) can be determined using the following equation: c cn = v sn v sn ?r cn ?f osc where v sn is the voltage ripple across c cn . a reasonable v sn is 5% to 10% of v sn . the reverse voltage rating of d sn should be higher than the sum of v sn and v in(max) . flyback converter: sense resistor selection in a flyback converter, when the power switch is turned on, the current flowing through the sense resistor (i sense ) is: i sense = i lp set the sense voltage at i lp(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 40mv i lp(peak) flyback converter: power mosfet selection for the flyback configuration, the mosfet is selected with a v dc rating high enough to handle the maximum v in , the reflected secondary voltage and the voltage spike due to the leakage inductance. approximate the required mosfet v dc rating using: bv dss > v ds(peak) where: v ds(peak) = v in(max) + v sn the power dissipated by the mosfet in a flyback con- verter is: p fet = i 2 m(rms) ? r ds(on) + 2 ? v 2 ds(peak) ? i l(max) ? c rss ? f osc /1a the first term in this equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet ? ja = t a + p fet ? ( jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. flyback converter: output diode selection the output diode in a flyback converter is subject to large rms current and peak reverse voltage stresses. a fast switching diode with a low forward drop and a low reverse leakage is desired. schottky diodes are recommended if the output voltage is below 100v. approximate the required peak repetitive reverse voltage rating v rrm using: v rrm > n s n p ?v in(max) + v out the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r ja the r ja to be used in this equation normally includes the r jc for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. flyback converter: output capacitor selection the output capacitor of the flyback converter has a similar operation condition as that of the boost converter. refer to the boost converter: output capacitor selection section for the calculation of c out and esr cout .
LT3759 20 3759fb the rms ripple current rating of the output capacitors in discontinuous operation can be determined using the following equation: i rms(cout),discontinuous i o(max ) ? 4 ? (3 ? d2) 3?d2 flyback converter: input capacitor selection the input capacitor in a flyback converter is subject to a large rms current due to the discontinuous primary current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the rms ripple current rating of the input capacitors in discontinuous operation can be determined using the following equation: i rms(cin),discontinuous p out(max) v in(min) ? ? 4 ? (3 ? d max ) 3?d max sepic converter applications the LT3759 can be configured as a sepic (single-ended primary inductance converter), as shown in figure 1. this topology allows for the input to be higher, equal, or lower than the desired output voltage. the conversion ratio as a function of duty cycle is: v out + v d v in = d 1 ? d in continuous conduction mode (ccm). in a sepic converter, no dc path exists between the input and output. this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ), the input voltage (v in ) and diode forward voltage (v d ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out + v d v in(min) + v out + v d sepic converter: inductor and sense resistor selection as shown in figure 1, the sepic converter contains two inductors: l1 and l2. l1 and l2 can be independent, but can also be wound on the same core, since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max) = i in(max) = i o(max ) d max 1C d max i l2(max) = i o(max ) in a sepic converter, the switch current is equal to i l1 + i l2 when the power switch is on, therefore, the maximum average switch current is defined as: i sw(max) = i l1(max) + i l2(max) = i o(max ) ? 1 1C d max and the peak switch current is: i sw(peak) = 1 + 2 ? ? ? ? ? ? ?i o(max ) ? 1 1C d max the constant in the preceding equations represents the percentage peak-to-peak ripple current in the switch, rela- tive to i sw(max) , as shown in figure 8. then, the switch ripple current i sw can be calculated by: d i sw =c?i sw(max) applications information
LT3759 21 3759fb the inductor ripple currents i l1 and i l2 are identical: d i l1 =d i l2 = 0.5 ? d i sw by making l1 = l2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) d i sw ?f osc ?d max = r sense ?v in(min) 0.01v ? f osc ?d max in a sepic converter, when the power switch is turned on, the current flowing through the sense resistor (i sense ) is the switch current. set the sense voltage at i sense(peak) to be minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 40mv i sw(peak) sepic converter: power mosfet selection for the sepic configuration, choose a mosfet with a v dc rating higher than the sum of the output voltage and input voltage by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the mosfet in a sepic converter is: p fet = i 2 sw(max) ?r ds(on) ?d max + (v in(min) + v out ) 2 ?i sw(max) ?c rss ? f osc 1a the first term in this equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. figure 8. the switch current waveform of a sepic converter 3759 f08 )i sw = h zi sw(max) i sw t dt s i sw(max) t s applications information the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of i l allows the use of low in- ductances, but results in higher input current ripple and greater core losses. it is recommended that falls in the range of 0.2 to 0.4. choose an inductor value based on operating frequency, input and output voltage to provide a current mode ramp on sense during the switch on-time of approximately 10mv magnitude. the inductor value (l1 and l2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? d i sw ?f osc ?d max = r sense ?v in(min) 0.5 ? 0.01v ? f osc ?d max for most sepic applications, the equal inductor values will fall in the range of 1h to 100h.
LT3759 22 3759fb for maximum efficiency, r ds(on) and c rss should be minimized. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet ? ja = t a + p fet ?( jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. sepic converter: output diode selection to maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. the average forward current in normal operation is equal to the output current, and the peak current is equal to: i d(peak ) = 1 + 2 ? ? ? ? ? ? ?i o(max ) ? 1 1 ? d max it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max ) ?v d and the diode junction temperature is: t j = t a + p d ?r ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter. please refer to the boost converter, output capacitor selection and boost converter, input capacitor selection sections. sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 1) should be rated for the maximum input voltage: c dc v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) i o(max ) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . inverting converter applications the LT3759 can be configured as a dual-inductor inverting topology, as shown in figure 9. the v out to v in ratio is: v out Cv d v in = d 1 ? d in continuous conduction mode (ccm). applications information figure 9. a simplified inverting converter r sense c dc v in c in l1 d1 c out v out 3759 f09 + gate gnd LT3759 sense l2 m1 + C + C +
LT3759 23 3759fb inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out Cv d v out Cv d Cv in(min) inverting converter: inductor, sense resistor, power mosfet, output diode and input capacitor selections the selections of the inductor, sense resistor, power mosfet, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections. inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost and sepic converters for similar output ripples. this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: v out(p ? p) = i l2 s esr cout + 1 8 s f osc s c out ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt- age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) > 0.3 ? d i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 9) should be larger than the maximum input voltage minus the output voltage (negative voltage): v cdc > v in(max) Cv out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max ) ? d max 1C d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . board layout the high speed operation of the LT3759 demands careful attention to board layout and component placement. the exposed pad of the package is the only gnd terminal of the ic, and is important for thermal management of the ic. therefore, it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground plane of the board. for the LT3759 to deliver its full output power, it is imperative that a good thermal path be pro- vided to dissipate the heat generated within the package. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. to prevent radiation and high frequency resonance prob- lems, proper layout of the components connected to the ic is essential, especially the power paths with higher di/ dt. the following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: ? in boost configuration, the high di/dt loop contains the output capacitor, the sensing resistor, the power mosfet and the schottky diode. applications information
LT3759 24 3759fb ? in flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the power mosfet and sensing resistor. the high di/dt secondary loop contains the output capacitor, the sec- ondary winding and the output diode. ? in sepic configuration, the high di/dt loop contains the power mosfet, sense resistor, output capacitor, schottky diode and the coupling capacitor. ? in inverting configuration, the high di/dt loop contains power mosfet, sense resistor, schottky diode and the coupling capacitor. check the stress on the power mosfet by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing, which can exceed the maximum specified voltage rating of the mosfet. if this ringing cannot be avoided, and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalancher- ated power mosfet. the small-signal components should be placed away from high frequency switching nodes. for optimum load regula- tion and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resis- tors near the LT3759 in order to keep the high impedance fbx node short. figure 10 shows the suggested layout of 1.8v to 3.3v input, 5v/2a output boost converter. applications information figure 10. the suggested boost converter layout 3759 f10 v out l1 vias to ground plane d1 c out1 c out2 c in 1 2 8 7 3 4 6 5 m1 r c r1 r2 c ss r t r3 r4 c vcc c drive c c1 c c2 LT3759 13 2 3 1 4 5 6 10 11 12 7 8 9 r s r pgood v in v in vias to v in gnd
LT3759 25 3759fb typical applications 1.8v to 3.3v input, 5v/2a output boost converter efficiency vs output current load step response at v in = 2.5v output current (a) 0.001 efficiency (%) 60 80 100 1 3759 ta02b 40 0.01 0.1 10 10 20 30 50 70 90 0 v in = 1.8v v in = 3.3v v out 500mv/div (ac) i out 1a/div 3759 ta02c 500s/div 1.6a 0.4a sense LT3759 v in drive v in 1.8v to 3.3v c in 47f 6.3v x5r r t 27.4k 300khz gate pgood fbx gnd intv cc en/uvlo sync rt ss vc l1 2.2h r3 59k r4 124k c ss 0.1f m1: vishay si414dj l1: toko fda1055-2r2m d1: vishay 6cwq06fn r c 7.5k c c1 22nf r1 15.8k 1% r2 34k 1% r s 5m 0.5w c c2 100pf c vcc 4.7f 10v x5r v out 5v 2a c out2 100f 6.3v x5r 3 3759 ta02a d1 m1 r5 10k
LT3759 26 3759fb typical applications 8v to 16v input, 24v/2a output boost converter efficiency vs output current load step response at v in = 12v output current (a) 0.001 efficiency (%) 60 80 100 1 3759 ta03b 40 0.01 0.1 10 10 20 30 50 70 90 0 v in = 8v v in = 16v v out 500mv/div (ac) i out 1a/div 3759 ta03c 500s/div 1.6a 0.4a sense LT3759 v in drive v in 8v to 16v c in 22f 25v x5r r t 27.4k 300khz gate pgood fbx gnd intv cc en/uvlo sync rt ss vc l1 10h r3 200k r4 43.2k c ss 0.1f r c 20k c c1 10nf r1 16.2k 1% r2 226k 1% r s 5m 0.5w c c2 100pf c vcc 4.7f 10v x5r v out 24v 2a c out2 22f 25v x5r 3759 ta03a c out1 33f 35v 2 d1 m1 r5 100k + m1: vishay siliconix si4840 bdy l1: wrth elektronik 7443321000 d1: vishay 6cwq06fn
LT3759 27 3759fb typical applications 1.8v to 5v input, 3.3v/3a output sepic converter efficiency vs output current load step response at v in = 2.5v v out 500mv/div (ac) i out 1a/div 3759 ta04c 500s/div 2.5a 0.5a output current (a) 0.001 efficiency (%) 60 80 100 1 3759 ta04b 40 0.01 0.1 10 10 20 30 50 70 90 0 v in = 2.5v sense LT3759 v in drive v in 1.8v to 5v c in 47f 10v 27.4k 300khz c dc 4.7f 10v, x5r, 2 gate pgood fbx gnd intv cc en/uvlo sync rt ss vc l1a l1b i l1a v sw i l1b 59k 124k 0.1f 3.01k 22nf 15.8k 1% 16.9k 1% 0.004 1w 4.7f 10v x5r v out 3.3v 2a, 1.8v v in 3v 3a, 3v < v in 5v c out 100f 6.3v x5r 3 3759 ta04a d1 m1 10k m1: vishay si7858bdp l1a, l1b: coiltronics drq127-4r7 d1: vishay 6cwq06fn
LT3759 28 3759fb typical applications 2.5v to 36v input, 12v/1a output sepic converter (automotive 12v regulator) efficiency vs output current load step response at v in = 12v frequency foldback waveforms when output short-circuits sense LT3759 v in drive v in 2.5v to 36v c in 4.7f 50v 4 41.2k 200khz c dc 4.7f 50v, x5r, 2 gate pgood fbx gnd intv cc en/uvlo sync rt ss vc l1a l1b i l1b i l1a 105k 118k 0.1f 7.5k 22nf 15.8k 1% 105k 1% 0.005 0.5w 4.7f 10v x5r v out 12v 0.5a, 2.5v v in 8v 2a, 8v < v in 36v c out2 10f 25v x5r 3759 ta05a c out1 47f 20v 4 d1 m1 100k + v sw m1: vishay siliconix si7460dp l1a, l1b: coiltronics drq127-150 d1: vishay 6cwq06fn output current (a) 0 efficiency (%) 90 95 100 1.5 2.5 3759 ta05b 85 0.5 1 2 80 75 v in = 12v v out 500mv/div (ac) i out 1a/div 3759 ta05c 500s/div 1.6a 0.4a v out 10v/div v sw 20v/div i l1a + l1b 5a/div 3759 ta05d 20s/div
LT3759 29 3759fb typical applications 5v to 15v input, C5v/3a output inverting converter efficiency vs output current load step response at v in = 10v frequency foldback waveforms when output short-circuits output current (a) 0.001 efficiency (%) 60 80 100 1 3759 ta06b 40 0.01 0.1 10 10 20 30 50 70 90 0 v in = 15v v in = 5v v out 500mv/div (ac) i out 2a/div 3759 ta06c 500s/div 4a 0.5a v out 5v/div v sw 10v/div i l1a + l1b 5a/div 3759 ta06d 20s/div sense LT3759 v in drive v in 5v to 15v c in 47f 16v x5r 27.4k 300khz gate pgood fbx gnd intv cc en/uvlo sync rt ss vc r2 105k r1 45.3k 0.1f 9.1k 10nf 15.8k 84.5k c dc 4.7f 25v, x5r, 2 5m 0.5w c vcc 4.7f 10v x5r v out C5v 3a, 5v v in 10v 4a, 10v < v in 15v c out 47f 6.3v, x5r 4 3759 ta06a m1 100k l1b 3.3h l1a 3.3h d1 m1: vishay siliconix si7848bdp l1a, l1b: coiltronics drq127-3r3 d1: vishay 6cwq03fn
LT3759 30 3759fb package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse12) 0911 rev f 0.53 t0.152 (.021 t.006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C?0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail b 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0s C 6s typ detail a detail a gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 t0.102 (.112 t.004) 2.845 t0.102 (.112 t.004) 4.039 t0.102 (.159 t.004) (note 3) 1.651 t0.102 (.065 t.004) 1.651 t0.102 (.065 t.004) 0.1016 t0.0508 (.004 t.002) 123456 3.00 t0.102 (.118 t.004) (note 4) 0.406 t0.076 (.016 t.003) ref 4.90 t0.152 (.193 t.006) detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 t0.127 (.035 t.005) 0.42 t0.038 (.0165 t.0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev f)
LT3759 31 3759fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 12/11 ss pull-up current min and typ values updated and intv cc current in shutdown typ value updated in electrical characteristics table. 3, 4 revised typical application drawing ta02a 25 b 4/12 revised typical applications schematic ta01a added un/uvlo rising spec 1 4
LT3759 32 3759fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0412 rev b ? printed in usa related parts typical application part number description comments lt3757 boost, flyback, sepic and inverting controller 2.9v v in 40v, current mode control, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e packages lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, current mode control, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e packages lt3957 boost, flyback, sepic and inverting converter with 5a, 40v switch 3v v in 40v, current mode control, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn package lt3958 boost, flyback, sepic and inverting converter with 3.3a, 84v switch 5v v in 80v, current mode control, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn package ltc3872 no r sense boost controller 2.75v v in 9.8v, tsot-23 and 2mm 3mm dfn-8 1.8v to 5v input, C5v/2a output inverting converter efficiency vs output current sense drive LT3759 v in v in 1.8v to 5v c in 47 f 10v x5r 27.4k 300khz c dc 4.7f 2 25v, x5r 1f 16v x5r gate fbx gnd intv cc en/uvlo sync pgood rt ss vc l1b 3.3h l1a, 3.3h 1:1 59k 124k 0.1f 9.1k 10nf 5m 0.5w 100k tie to gnd if not used c vcc 4.7f 10v x5r v out C5v 1a, 1.8v v in 2.5v 2a, 2.5v < v in 5v c out 100f 6.3v, x5r 2 3759 ta07a d2 m1 d1 m1: vishay siliconix si74116dy l1a, l1b: coiltronics drq127-3r3 d1: vishay 6cwq03fn d2: philips pmeg2005ej 84.5k 15.8k output current (a) 0 efficiency (%) 95 100 1.5 3759 ta07b 0.5 1 2.52 75 80 85 90 70 v in = 5v v in = 2.5v

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